Applicants' related copending U.S. Pat. No. 8,093,604, entitled “Engineered Structure for Solid State Light Emitters,” issued to Chik et al.; U.S. Pat. No. 7,800,117, entitled “Pixel Structure for a Solid State Light Emitting Device,” issued to Chik et al.; and U.S. Pat. No. 8,089,080, entitled “Engineered Structure for High Brightness Solid-State Light Emitters,” issued to Calder et al., which are incorporated herein by reference, disclose light emitting device structures and methods of fabrication of light emitting device structures from silicon or other group IV materials. In particular, high brightness, light emitting device structures are disclosed that comprise thin active layers, i.e., light emitting layers, comprising luminescent centers which may be electrically excited, such as rare earth ions in a rare earth oxide or other suitable host matrix. The host matrix may comprise a dielectric, such as silicon dioxide, silicon nitride, silicon oxynitride, silicon aluminum oxynitride (SiAlON), aluminum oxide, or other materials, such as disclosed in the above-referenced copending applications.
For excitation efficiency, a drift layer, i.e., an electron acceleration layer, comprising, for example, undoped silicon dioxide or silicon nitride, is provided adjacent each active layer. For high brightness light emitters, engineered structures are provided comprising a plurality of active layer and drift layer pairs, in which each drift layer has a thickness, dependent on the applied electric field, related to a desired excitation energy of an adjacent active layer. Multilayer light emitting structures may be provided, for example, comprising one or more active layers comprising rare earth doped silicon dioxide or silicon nitride, and corresponding drift layers comprising undoped silicon dioxide or silicon nitride. Active layers are thin and may be in the range from one monolayer (1 atomic layer) to 10 nm thick. Drift layers are typically 2-10 nm thick, depending on the applied electric field, to provide a sufficient thickness for acceleration of electrons for appropriate energy matching. Light emitting structures of this type may be fabricated as large area emitters or as pixel structures. Structures may comprise one active layer/drift layer pair or many, e.g., 24, layer pairs emitting one or more colors, to provide light emission of a desired Color Rendering Index (CRI).
With reference to FIG. 1, a light emitting device structure 1, similar to that described in the above-referenced copending U.S. patent applications, comprises a multilayer emitter structure 2 including a plurality of active layer/drift layer pairs, i.e., thin active layers of rare earth doped silicon nitride 3 and silicon dioxide drift layers 4, formed on a silicon substrate 6 with a back contact electrode 7. Also provided is a top electrode 8 comprising a transparent conducting oxide, such as indium tin oxide. Light emission from the multilayer emitter structure 1 may be electrically excited by application of a suitable AC or DC voltage 5 to the emitter layer structure 2 between the back contact electrode 7 and the top electrode 8.
For light emitting structures 1, as disclosed in the above mentioned references, which operate at relatively high electric fields, i.e., 5 MV/cm or more, high quality dielectrics with low trap density are included for reliability and extended lifetime. For high brightness and luminous efficiency, careful control of layer thicknesses is desirable. Such structures have been fabricated by plasma enhanced chemical vapor deposition (PECVD), for example.
Suitable rare earth containing oxides, or rare earth doped oxides or other dielectrics, can be formed by any of a number of techniques, such as ion implantation, chemical vapor deposition (CVD), physical vapor deposition, i.e., sputtering, spin-on (sol gel) techniques, beam deposition, laser deposition, or any of a large number of similar chemical or physical deposition techniques. Although epitaxial processes grow nano-structured single crystal semiconductor layers, e.g., for multiquantum well (MQW) semiconductor lasers with quantum well (QW) thicknesses on the order of 3-5 nm, these processes are typically applied for deposition of crystalline materials and are generally not applicable for amorphous, i.e., non-crystalline, dielectric layers. Methods, such as chemical vapor deposition (CVD), achieve high quality, uniform single layers of thin dielectrics, or a few thin film dielectric layers, i.e., the number of layers N=2 or 3, for such structures as transistor gate stacks. However, achieving high quality multilayer stacks (N>3) of thin films of amorphous or non-crystalline materials poses some challenges to known commercial chemical vapor deposition processes for volume production at reasonable cost.
Although light emitting device structures, such as shown in FIG. 1, have been fabricated by PECVD, for larger scale fabrication of multilayer light emitting structures, a suitable production class tool is suggested that is capable of deposition of high quality oxides and nitrides. In these respects, a low pressure (LP) CVD process, i.e., thermal CVD, for deposition of higher quality dielectrics offers some advantages over a PECVD process.
For commercial production of high quality, thin dielectrics such as silicon dioxide used for gate oxides for electronic devices, industry standard processes use chemical vapor deposition (CVD). That is, silicon dioxide and silicon nitride are typically produced by low pressure CVD from a mixture of reactant gases comprising a silicon source gas, typically silane (SiH4), dichlorosilane (SiH2Cl2), or TEOS (tetra-ethyl ortho silicate (Si(OC2H5)4) with an oxidation source gas, e.g., oxygen (O2) or nitrous oxide (N2O), or a nitridation source gas, e.g., ammonia (NH3) or nitrogen (N2), as appropriate. The reaction is thermally driven, at a relatively high temperature, e.g., 400-900 DC. Examples of systems and processes and examples of reactant gases and process conditions for chemical vapor deposition of silicon dioxide, silicon nitride, and silicon oxynitride are disclosed, for example, in U.S. Pat. Nos. 6,713,127; 6,884,464; and 7,465,669, issued to Iyer et al. (Applied Materials). To achieve uniformity and flatness of each layer in a multilayer structure, an optional post deposition treatment or passivation with the oxidation or nitridation source gas is also disclosed. That is, after deposition of a desired layer thickness, the flow of silicon source gas is turned off (or diverted) and the surface of the deposited layer is then exposed to a flow of nitridation or oxidation source gas, i.e., ammonia or nitrous oxide. This post treatment of the deposited layer with oxidation or nitridation source gas is explained in U.S. Pat. Nos. 6,713,127 and 6,884,464 as terminating unreacted silicon sites to maximize uniformity and minimize surface roughness of the deposited layers.
However, attempts to fabricate larger area, thin film dielectric layers for multilayer light emitting structures, as described above, using available commercial thermal CVD processes and equipment, and reactant gas mixtures and process conditions, such as those described in the aforementioned patents, do not provide sufficient control of the layer thicknesses, uniformity, and layer-to-layer reproducibility for such light emitting structures. In fabricating a light emitting device structure wherein active layers comprise rare earth doped silicon nitride, and drift layers comprise silicon dioxide, there is breakdown of the layer structure after deposition of the first few layers on a silicon substrate. For example, FIG. 2 shows a transmission electron micrograph (TEM) cross section through a multilayer structure comprising five periods, i.e., five layer pairs, deposited using conventional disilane chemistry and process sequence, and including a step of post-deposition treatment with the oxidation or nitridation source gas, as described above.
The photomicrograph in FIG. 2 illustrates an example of the multilayer emitter structure 2, which comprises a plurality of thin layers of silicon nitride 3 and silicon dioxide 4, formed on a silicon substrate 6. In FIG. 2, the silicon nitride layers 3 appear with darker contrast than the silicon dioxide layers 4. The multilayer emitter structure 2 was deposited by a process of thermal chemical vapor deposition (CVD) at low pressure, using disilane as the silicon source gas, and an oxidation source gas comprising N2O or a nitridation source gas comprising NH3, to produce the silicon dioxide or silicon nitride layers, respectively. After suitable preparation of the silicon substrate 6, deposition of a layer of silicon dioxide 4 or silicon nitride 3 proceeds by introducing a suitable mixture of reactant gases, together with an inert carrier gas into the CVD reaction chamber at an appropriate temperature and pressure. The substrate 6 is exposed to the reactant gas mixture for a time sufficient to deposit a desired thickness of dielectric, i.e., silicon nitride 3 or silicon dioxide 4. When the desired thickness of dielectric is reached, the disilane flow is switched off or diverted, and the flow of nitridation or oxidation source gas, e.g., N2O or NH3, is continued for post treatment, i.e., to terminate reactive silicon and passivate the surface of the deposited dielectric layer 3 or 4. After purging the chamber with inert carrier gas, the reactant gas mixture for deposition of the next layer is introduced into the chamber, and so on. This allows a number of silicon nitride layers 3 and silicon dioxide layers 4 of a predetermined thickness to be deposited sequentially.
However, as will be seen from FIG. 2, although reasonable uniformity of the layer thickness is obtained for the first silicon dioxide layer 4, the layer structure begins to break down as more layers are deposited. Several layers into the structure, significant surface structure and roughness of each layer is apparent, which propagates through subsequently deposited layers. Thus, for example, in a large area multilayer structure, such as for a light emitting device structure 2 as shown schematically in FIG. 1, that includes, for example, 48 layers, i.e., 24 layer pairs, of active silicon nitride layers 3 comprising a luminescent species, and respective drift silicon dioxide layers 4, this structure is far from ideal. The light emitting structure 2 in FIG. 2 shows surface roughness exceeding 1 nm. In particular, in a light emitting structure, careful control of the drift layer thickness is desirable for controlling excitation energy in operation of the device, and because such devices operate at relatively high fields, high quality oxides or nitrides, free of defects, are used for reliability and extended lifetime. As apparent from FIG. 2, surface “roughness” or discontinuities in the layers structure are as large as the thickness of the layer. Consequently this process, even with post treatment of the deposited layers with the oxidation or nitridation source gas, cannot meet the specifications for a multilayer light emitting device structure described above, including sub-nanometer surface roughness.
Consequently, processes are suggested for deposition of multilayer light emitting structures comprising nano-layer dielectrics, particularly for layers less than 10 nm thick, where careful control of layer uniformity, thickness, surface roughness or flatness, and layer-to-layer reproducibility is desired.
It is desirable to provide for uniformity and flatness of dielectric layers for light emitting structures and other semiconductor devices.
Thus, alternative or improved materials, structures, and/or methods of fabrication for solid-state light emitters, particularly for applications requiring higher brightness, luminous efficacy and reliability, such as solid-state lighting or devices, are desired.